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Complex instruction set computer

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a computer architecture predating or contrasting with reduced instruction set computer
This article includes a list of references , but its sources remain unclear because it has insufficient inline citations . Please help to improve this article by introducing more precise citations. (January 2012) ( Learn how and when to remove this template message )

A complex instruction set computer (CISC /ˈsɪsk/ ) is a computer in which single instructions can execute several low-level operations (such as a load from memory , an arithmetic operation , and a memory store ) or are capable of multi-step operations or addressing modes within single instructions. The term was retroactively coined in contrast to reduced instruction set computer (RISC) [1] [2] and has therefore become something of an umbrella term for everything that is not RISC, from large and complex mainframe computers to simplistic microcontrollers where memory load and store operations are not separated from arithmetic instructions. A modern RISC processor can therefore be much more complex than, say, a modern microcontroller using a CISC-labeled instruction set , especially in the complexity of its electronic circuits, but also in the number of instructions or the complexity of their encoding patterns. The only typical differentiating characteristic is that most RISC designs use uniform instruction length for almost all instructions, and employ strictly separate load/store-instructions.

Examples of instruction set architectures that have been retroactively labeled CISC are System/360 through z/Architecture , the PDP-11 and VAX architectures, Data General Nova and many others. Well known microprocessors and microcontrollers that have also been labeled CISC in many academic publications include the Motorola 6800 , 6809 and 68000 -families; the Intel 8080 , iAPX432 and x86 -family; the Zilog Z80 , Z8 and Z8000 -families; the National Semiconductor 32016 and NS320xx -line; the MOS Technology 6502 -family; the Intel 8051 -family; and others.

Some designs have been regarded as borderline cases by some writers. For instance, the Microchip Technology PIC has been labeled RISC in some circles and CISC in others. The 6502 and 6809 have both been described as “RISC-like”, although they have complex addressing modes as well as arithmetic instructions that operate on memory, contrary to the RISC-principles.


  • 1 Historical design context
    • 1.1 Incitements and benefits
      • 1.1.1 New instructions
    • 1.2 Design issues
      • 1.2.1 The RISC idea
      • 1.2.2 Superscalar
      • 1.2.3 CISC and RISC terms
  • 2 See also
  • 3 References
  • 4 Further reading
  • 5 External links

Historical design context[ edit ]

Incitements and benefits[ edit ]

Before the RISC philosophy became prominent, many computer architects tried to bridge the so-called semantic gap , i.e., to design instruction sets that directly support high-level programming constructs such as procedure calls, loop control, and complex addressing modes , allowing data structure and array accesses to be combined into single instructions. Instructions are also typically highly encoded in order to further enhance the code density. The compact nature of such instruction sets results in smaller program sizes and fewer (slow) main memory accesses, which at the time (early 1960s and onwards) resulted in a tremendous saving on the cost of computer memory and disc storage, as well as faster execution. It also meant good programming productivity even in assembly language , as high level languages such as Fortran or Algol were not always available or appropriate. Indeed, microprocessors in this category are sometimes still programmed in assembly language for certain types of critical applications[ citation needed ].

New instructions[ edit ]

In the 1970s, analysis of high-level languages indicated some complex machine language implementations and it was determined that new instructions could improve performance. Some instructions were added that were never intended to be used in assembly language but fit well with compiled high-level languages. Compilers were updated to take advantage of these instructions. The benefits of semantically rich instructions with compact encodings can be seen in modern processors as well, particularly in the high-performance segment where caches are a central component (as opposed to most embedded systems ). This is because these fast, but complex and expensive, memories are inherently limited in size, making compact code beneficial. Of course, the fundamental reason they are needed is that main memories (i.e., dynamic RAM today) remain slow compared to a (high-performance) CPU core.

Design issues[ edit ]

While many designs achieved the aim of higher throughput at lower cost and also allowed high-level language constructs to be expressed by fewer instructions, it was observed that this was not always the case. For instance, low-end versions of complex architectures (i.e. using less hardware) could lead to situations where it was possible to improve performance by not using a complex instruction (such as a procedure call or enter instruction), but instead using a sequence of simpler instructions.

One reason for this was that architects ( microcode writers) sometimes “over-designed” assembly language instructions, including features which could not be implemented efficiently on the basic hardware available. There could, for instance, be “side effects” (above conventional flags), such as the setting of a register or memory location that was perhaps seldom used; if this was done via ordinary (non duplicated) internal buses, or even the external bus, it would demand extra cycles every time, and thus be quite inefficient.

Even in balanced high-performance designs, highly encoded and (relatively) high-level instructions could be complicated to decode and execute efficiently within a limited transistor budget. Such architectures therefore required a great deal of work on the part of the processor designer in cases where a simpler, but (typically) slower, solution based on decode tables and/or microcode sequencing is not appropriate. At a time when transistors and other components were a limited resource, this also left fewer components and less opportunity for other types of performance optimizations.

The RISC idea[ edit ]

The circuitry that performs the actions defined by the microcode in many (but not all) CISC processors is, in itself, a processor which in many ways is reminiscent in structure to very early CPU designs. In the early 1970s, this gave rise to ideas to return to simpler processor designs in order to make it more feasible to cope without (then relatively large and expensive) ROM tables and/or PLA structures for sequencing and/or decoding. The first (retroactively) RISC-labeled processor ( IBM 801  – IBM ‘s Watson Research Center, mid-1970s) was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or engine, in CISC designs, but also became the processor that introduced the RISC idea to a somewhat larger public. Simplicity and regularity also in the visible instruction set would make it easier to implement overlapping processor stages ( pipelining ) at the machine code level (i.e. the level seen by compilers). However, pipelining at that level was already used in some high performance CISC “supercomputers” in order to reduce the instruction cycle time (despite the complications of implementing within the limited component count and wiring complexity feasible at the time). Internal microcode execution in CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to the basic structure of RISC processors.

Superscalar[ edit ]

In a more modern context, the complex variable-length encoding used by some of the typical CISC architectures makes it complicated, but still feasible, to build a superscalar implementation of a CISC programming model directly; the in-order superscalar original Pentium and the out-of-order superscalar Cyrix 6×86 are well known examples of this. The frequent memory accesses for operands of a typical CISC machine may limit the instruction level parallelism that can be extracted from the code, although this is strongly mediated by the fast cache structures used in modern designs, as well as by other measures. Due to inherently compact and semantically rich instructions, the average amount of work performed per machine code unit (i.e. per byte or bit) is higher for a CISC than a RISC processor, which may give it a significant advantage in a modern cache based implementation.

Transistors for logic, PLAs, and microcode are no longer scarce resources; only large high-speed cache memories are limited by the maximum number of transistors today. Although complex, the transistor count of CISC decoders do not grow exponentially like the total number of transistors per processor (the majority typically used for caches). Together with better tools and enhanced technologies, this has led to new implementations of highly encoded and variable length designs without load-store limitations (i.e. non-RISC). This governs re-implementations of older architectures such as the ubiquitous x86 (see below) as well as new designs for microcontrollers for embedded systems , and similar uses. The superscalar complexity in the case of modern x86 was solved by converting instructions into one or more micro-operations and dynamically issuing those micro-operations, i.e. indirect and dynamic superscalar execution; the Pentium Pro and AMD K5 are early examples of this. It allows a fairly simple superscalar design to be located after the (fairly complex) decoders (and buffers), giving, so to speak, the best of both worlds in many respects. This technique is also used in IBM z196 and later z/Architecture microprocessors.

CISC and RISC terms[ edit ]

The terms CISC and RISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly (or tightly) pipelined x86 implementations, the 486 designs from Intel , AMD , Cyrix , and IBM , supported every instruction that their predecessors did, but achieved maximum efficiency only on a fairly simple x86 subset that was only a little more than a typical RISC instruction set (i.e. without typical RISC load-store limitations). The Intel P5 Pentium generation was a superscalar version of these principles. However, modern x86 processors also (typically) decode and split instructions into dynamic sequences of internally buffered micro-operations , which not only helps execute a larger subset of instructions in a pipelined (overlapping) fashion, but also facilitates more advanced extraction of parallelism out of the code stream, for even higher performance.

Contrary to popular simplifications (present also in some academic texts[ which? ]), not all CISCs are microcoded or have “complex” instructions. As CISC became a catch-all term meaning anything that’s not a load-store (RISC) architecture, it’s not the number of instructions, nor the complexity of the implementation or of the instructions themselves, that define CISC, but the fact that arithmetic instructions also perform memory accesses.[ citation needed ] Compared to a small 8-bit CISC processor, a RISC floating-point instruction is complex. CISC does not even need to have complex addressing modes; 32 or 64-bit RISC processors may well have more complex addressing modes than small 8-bit CISC processors.

A PDP-10 , a PDP-8 , an Intel 80386 , an Intel 4004 , a Motorola 68000 , a System z mainframe, a Burroughs B5000 , a VAX , a Zilog Z80000 , and a MOS Technology 6502 all vary wildly in the number, sizes, and formats of instructions, the number, types, and sizes of registers, and the available data types. Some have hardware support for operations like scanning for a substring, arbitrary-precision BCD arithmetic, or transcendental functions , while others have only 8-bit addition and subtraction. But they are all in the CISC category because they have “load-operate” instructions that load and/or store memory contents within the same instructions that perform the actual calculations. For instance, the PDP-8, having only 8 fixed-length instructions and no microcode at all, is a CISC because of how the instructions work, PowerPC, which has over 230 instructions (more than some VAXes), and complex internals like register renaming and a reorder buffer, is a RISC, while Minimal CISC has 8 instructions, but is clearly a CISC because it combines memory access and computation in the same instructions.

See also[ edit ]

  • icon Computer science portal
  • Computer architecture
  • ZISC
  • VLIW
  • Microcode
  • Comparison of instruction set architectures

References[ edit ]

  1. ^ Patterson, D. A. ; Ditzel, D. R. (October 1980). “The case for the reduced instruction set computer”. SIGARCH Computer Architecture News. ACM . 8 (6): 25–33. doi : 10.1145/641914.641917 .

  2. ^ Lakhe, Pravin R. (June 2013). “A Technology in Most Recent Processor is Complex Reduced Instruction Set Computers (CRISC): A Survey” (PDF). International Journal of Innovation Research and Studies. pp. 711–715. Archived from the original (PDF) on July 14, 2015.
  • Tanenbaum, Andrew S. (2006) Structured Computer Organization, Fifth Edition, Pearson Education, Inc. Upper Saddle River, NJ.

This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the “relicensing” terms of the GFDL , version 1.3 or later.

Further reading[ edit ]

  • Mano, M. Morris. Computer System Architecture (3rd Edition). ISBN   978-0131755635 .

External links[ edit ]

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        CISC (complex instruction set computer or computing)

        Posted by: Margaret Rouse



        Contributor(s): Steve Brazier and Hrvoje Cekolj

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        The term “CISC” (complex instruction set computer or computing) refers to computers designed with a full set of computer instructions that were intended to provide needed capabilities in the most efficient way. Later, it was discovered that, by reducing the full set to only the most frequently used instructions, the computer would get more work done in a shorter amount of time for most applications. Since this was called reduced instruction set computing ( RISC ), there was now a need to have something to call full-set instruction computers – thus, the term CISC.

        The PowerPC microprocessor, used in IBM’s RISC System/6000 workstation and Macintosh computers, is a RISC microprocessor. Intel’s Pentium microprocessors are CISC microprocessors. RISC takes each of the longer, more complex instructions from a CISC design and reduces it to multiple instructions that are shorter and faster to process.

        This was last updated in September 2005

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        What is The Difference Between RISC and CISC Architecture

        • Electronics


        The architecture of the Central Processing Unit (CPU) operates the capacity to function from “Instruction Set Architecture” to where it was designed. The architectural design of the CPU is Reduced instruction set computing (RISC) and Complex instruction set computing (CISC). CISC has the capacity to perform multi-step operations or addressing modes within one instruction set. It is the CPU design where one instruction works several low-level acts. For instance, memory storage, loading from memory, and an arithmetic operation. Reduced instruction set computing is a Central Processing Unit design strategy based on the vision that basic instruction set gives a great performance when combined with a microprocessor architecture which has the capacity to perform the instructions by using some microprocessor cycles per instruction. This article discusses the difference between the RISC and CISC architecture. The hardware part of the Intel is named as Complex Instruction Set Computer (CISC), and Apple hardware is Reduced Instruction Set Computer (RISC).


        Difference between RISC and CISC Architecture

        Before we discuss the differences between the  RISC and CISC architecture let us know about the concepts of RISC and CISC

        What is RISC?

        A reduced instruction set computer is a computer which only uses simple commands that can be divided into several instructions which achieve low-level operation within a single CLK cycle, as its name proposes “Reduced Instruction Set”.

        RISC Architecture

        The term RISC stands for ‘’Reduced Instruction Set Computer’’. It is a CPU design plan based on simple orders and acts fast.

        RISC Architecture
        RISC Architecture

        This is small or reduced set of instructions. Here, every instruction is expected to attain very small jobs. In this machine, the instruction sets are modest and simple, which help in comprising more complex commands. Each instruction is of the similar length; these are wound together to get compound tasks done in a single operation. Most commands are completed in one machine cycle. This pipelining is a crucial technique used to speed up RISC machines.

        What is CISC?

        A complex instruction set computer is a computer where single instructions can perform numerous low-level operations like a load from memory, an arithmetic operation, and a memory store or are accomplished by multi-step processes or addressing modes in single instructions, as its name proposes “Complex Instruction Set ”.

        CISC Architecture

        The term CISC stands for ‘’Complex Instruction Set Computer’’. It is a CPU design plan based on single commands, which are skilled in executing multi-step operations.

        CISC Architecture
        CISC Architecture

        CISC computers have small programs. It has a huge number of compound instructions, which takes a long time to perform. Here, a single set of instruction is protected in several steps; each instruction set has additional than 300 separate instructions. Maximum instructions are finished in two to ten machine cycles. In CISC, instruction pipelining is not easily implemented.

        Difference between RISC and CISC Architecture

        Difference between RISC and CISC
        Difference between RISC and CISC




        1. RISC stands for Reduced Instruction Set Computer.1. CISC stands for Complex Instruction Set Computer.
        2. RISC processors have simple instructions taking about one clock cycle. The average clock cycle per instruction (CPI) is 1.52. CSIC processor has complex instructions that take up multiple clocks for execution. The average clock cycle per instruction (CPI) is in the range of 2 and 15.
        3. Performance is optimized with more focus on software3. Performance is optimized with more focus on hardware.
        4. It has no memory unit and uses a separate hardware to implement instructions..4. It has a memory unit to implement complex instructions.
        5. It has a hard-wired unit of programming.5. It has a microprogramming unit.
        6. The instruction set is reduced i.e. it has only a few instructions in the instruction set. Many of these instructions are very primitive.6. The instruction set has a variety of different instructions that can be used for complex operations.
        7. The instruction set has a variety of different instructions that can be used for complex operations.7. CISC has many different addressing modes and can thus be used to represent higher-level programming language statements more efficiently.
        8. Complex addressing modes are synthesized using the software.8. CISC already supports complex addressing modes
        9. Multiple register sets are present9. Only has a single register set
        10. RISC processors are highly pipelined10. They are normally not pipelined or less pipelined
        11. The complexity of RISC lies with the compiler that executes the program11. The complexity lies in the microprogram
        12. Execution time is very less12. Execution time is very high
        13. Code expansion can be a problem13. Code expansion is not a problem
        14. Decoding of instructions is simple.14. Decoding of instructions is complex
        15. It does not require external memory for calculations15. It requires external memory for calculations
        16. The most common RISC microprocessors are Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC.16. Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family, AMD and Intel x86 CPUs.
        17. RISC architecture is used in high-end applications such as video processing, telecommunications and image processing.17. CISC architecture is used in low-end applications such as security systems, home automation, etc.

        This article discusses the concepts of RISC, CISC and its differences. We hope that you have got a better understanding of this concept. Furthermore, for any doubts regarding this concept, or implementation of any electrical and electronic projects, please give your feedback by commenting on the comment section below

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        1. thanks for risc and cisc very helpful

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        2. Nice…..this help me prepare my exams….

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          2. nice

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